opencores

1. opencores. org there are a lot of features available here. We can find the very good PLD kernel in 8051 kernel. after entering, select a project or enter http // www.opencores.org/browse.cgi/by_category . http://www.opencores.org/polls.cgi/list Opencores is a loose collection of people who are interested in developing hardware, with a similar ethos to the free software movement. currently the emph

Introduction The book to go to school to finally feel shallow, never know this matter to preach. The contents of the previous sections are based on ready-made things, with a ready-made comprehensive SVF file, Ormon is also compiled in advance, Linux is also transplanted well, these are opencores for us to fix. Of course, it is not said to use ready-made no meaning, meaning is very large, that is, an intuitive, direct feeling. If you want to further r

%A6Banana pie: http://www.banana-pi.org.cn/cubieboard:http://cubieboard.org/Cubieboard Chinese Forum: http://www.cubie.cc/forum.phpHikey (lemaker): HTTP://WWW.LEMAKER.ORG/CN Opencores (the world's largest web site and community for developing open source hardware IP cores): http://opencores.org/OPENHW Open Source Hardware community: http://www.openhw.org/Beijing Create a guest space: http://www.bjmakerspace.com/Firewood Create guest space: http://www.

I will upload my new book "Write CPU by myself" (not published yet). Today is 13th articles. I try to write them every Thursday. 4.4 create the MIPs compiling environment The openmips processor is designed to be compatible with the mips32 instruction set architecture. Therefore, you can use the existing GNU development tool chain under the mips32 architecture. This section describes how to install and use the GNU development tool chain and how to create makefile files to compile the test progra

Erection and Simulation (DE2,DE2-70) I recently got OpenRISC, someone was working on it, and wrote a master thesis, I've uploaded: http://download.csdn.net/detail/rill_zhen/5303401 The following content should be based on the guidance of the paper completed, but not my completion, so reproduced as follows: Do a or1200 minimum system, Or1200+wishbone+ram+gpio, on the DE2 platform to read the value of the SW and then LEDR to show the simple program. I'll record some of the major steps. In

project, need to have a deep understanding of the implementation of the CPU, looking for a long time, did not find a more ideal reference. Ask for yourself, hehe, so you want to analyze an open source of the CPU code. Hope to put the theory into reality. A person's power is weak, here also hope that interested colleagues to participate in. 1.1 Intuitive feeling Open source CPU, I chose the opencores development of the or1200. SOURCE I have upload

effectively solve the I2C stability problem!'Define deb_i2c_len 4 // note: the source code is set based on the system. The source code is from the open source website.// 3.1) opencores 'i2c slave, debounce SDA and SCLAlways @ (posedge fast_clk or negedge resetn)BeginIf (! Resetn)BeginSdapipe Sdadeb Sclpipe Scldeb EndElseBeginSdapipe Sclpipe If ( sclpipe ['deb _ I2C_LEN-1: 1] = 1 'b1)Scldeb Else if (| sclpipe ['deb _ I2C_LEN-1: 1] = 1' B0)Scldeb If (

Introduction As mentioned above, "If SOC is compared to a person," the debug subsystem is equivalent to a doctor who can detect the health of the body. This section briefly analyzes the debug subsystem of orpsoc. The debug system serves as two main tasks. In addition to debugging, it is also responsible for programming Flash.1. subsystem structure 2. Structure Description The entire debug system can be simply divided into two parts: the upper part and the lower part. The upper and lower parts

1. opencores.orgHere is a very much, very good pld of the kernel, the 8051 kernel can be found inside.After entering, select Project or enter by Http//www.opencores.org/browse.cgi/by_category.For people who want to learn about this industry dynamics, you can look at it poll.Http://www.opencores.org/polls.cgi/listOpencores is a loose collection of people who be interested in developing hardware, with a similar ethos to the free soft Ware movement. Currently the emphasis is on digital modules call

1. What is the difference between risc-v and other open architecturesIf judging only from the two points "free" or "open", the RISC-V architecture is not the first to do a free or open processor architecture.Before we begin, we'll start by discussing a few representative open architectures to analyze the differences in the RISC-V architecture and why other open architectures have failed to achieve enough success. Civilian hero--openriscOpenRISC is an open source RISC processor provided by the

(Cong Jingsheng LAB) Objective Q is a blog of shakith Fernando, mainly used for image processing FPGA and GPU parallel acceleration. His laboratory is located in the laboratory of parallel computing at the University of eenhofine, Netherlands. http://parse.ele.tue.nl/ University of Technology Eindhoven FPGA 2015 International Seminar Linaro File System Bologna University FPGA stereo vision Home: OpenCores, an open-source fpga

controller││││opencores i²c controller││││ asPlatform Device││││Interface││││Xilinx i²c controller│││└────v (+) ────────────────────────────────────────────────────────────────┘│├────────────────────────────────────── ──────────────────────────────────────┤││└────────────────────────────────────────────────────────────────────────────┘ Four. Turn on the AT24CXX series EEPROM driver:1because the Linux kernel already contains the drivers for the At24cx

I recently got OpenRISC, someone was working on it, and wrote a master thesis, I've uploaded: http://download.csdn.net/detail/rill_zhen/5303401 The following content should be based on the guidance of the paper completed, but not my completion, so reproduced as follows: Connect an article (original) based on or1200 minimum SOPC system (ii)--QUARTUII project and DE2 platform download Now add the serial port to the or1200 minimum system. Simulate first, then verify on DE2, and show Hello world!

Introduction Learning and studying or,wishbone is a problem that cannot be bypassed. This section will do a simple experiment to further deepen the understanding of the wishbone bus. 6.1 Bus Timing Please refer to the official spec and link below: Http://opencores.org/opencores,wishbone Report: Http://blog.csdn.net/column/details/ce123-wishbone.html 6.2 Experimental Contents A master, a slave,master by wishbone passing data (two operands) to t

OpenRISC is a good extension of open source computer architecture. Tools are also more complete, for example, Compiler,debugger,architecture Simulator,rtl simulator ... These tool are all there, and are opensource and have great flexibility. The best way to learn a technology is to use it and modify it. (The best way to learn and understandthe OpenRISC are to use It-rill_zhen). This section describes the building of a development environment. 3.1 References Some document and web link can ref